Field of the Invention
The invention relates to a circuit for synchronizing signals during the exchange of information between circuits, in particular between computer chips, of a system of circuits, having a delay locked loop (DLL) circuit for synchronizing the internal clock between a respective circuit and the external clock of the circuit system according to the phase difference between these two clocks in a manner dependent on phase changes in the signals. The response sensitivity of the DLL circuit being defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events.
Computer chips are operated with ever faster clock frequencies. Information is exchanged between the computer chips with signals that have to comply with defined timing specifications. The timing margins available in this case decrease at increasingly faster clock frequencies. Therefore, with increasingly faster clock frequencies, the signals which are transmitted in the context of the exchange of information between the computer chips have to be synchronized ever more accurately with respect to one another.
The task of the synchronization discussed is performed by a delay locked loop circuit (referred to below as a DLL circuit for short) implemented on the respective computer chip. The DLL circuit synchronizes the internal clock within the computer chip with the clock of the circuit system or the system of computer chips. For this purpose, the DLL circuit contains a phase detector which determines the phase difference between the internal clock of the computer chip and the external clock of the overall system. Furthermore, the DLL circuit contains variable delay elements (also referred to below as VCDL) that are connected or disconnected as required.
In order that the DLL circuit does not connect or disconnect delay elements in the case of every phase change, which, in principle, can occur in every clock cycle, a filter is provided in the DLL circuit. The function of the filter is to drive an output signal only after repeated arrival of an input signal and thus to trigger the synchronization by the DLL circuit only after a specific number of clock cycles. The filter is generally implemented on the basis of a plurality of counters and it determines, as discussed above, the sensitivity of the DLL circuit to phase changes. The number of counters in the filter depends on the specific computer chip and the overall system of computer chips and has hitherto formed an invariable quantity.
It is accordingly an object of the invention to provide a circuit for synchronizing signals during the exchange of information between circuits which overcomes the above-mentioned disadvantages of the prior art devices of this general type, whose sensitivity to phase changes is adjustable.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for synchronizing signals during an exchange of information between circuits of a circuit system. The configuration contains a delay locked loop circuit for synchronizing an internal clock of one of the circuits and an external clock of the circuit system according to a phase difference between the internal clock and the external clock in a manner dependent on phase changes in the signals. The delay locked loop circuit has a filter for defining a response sensitivity of the delay locked loop circuit. The filter enables a renewed synchronization only after an arrival of a plurality of phase change events. The filter has a variable configuration and includes a plurality of counters for generating a synchronization enable signal, and a logic circuit connected to and activating/deactivating the counters.
Accordingly, in contrast to the prior art, which provides a fixed filter configuration, according to the invention the filter contained in the DLL circuit is of a variable configuration. Depending on the construction of the filter, various measures are taken into consideration for altering the filter characteristics. For the case where the filter contains a plurality of counters for generating a synchronization enable signal, the invention provides a logic circuit for activating/deactivating the counters.
The setting of the sensitivity of the DLL circuit to phase changes of input signals plays a significant part in the preliminary stages of the enabling of computer chips or generally of circuits which require a synchronization in order to set the synchronization to the required response sensitivity in a targeted manner before the control operation with a defined response sensitivity. As soon as this setting has been effected, the logic circuit for setting the response sensitivity of the DLL circuit can be deactivated, if appropriate by fuses.
In addition to the principal advantage according to which the synchronization between the computer chips of the system of computer chips can be optimally set according to the invention in the preliminary stages of the control operation, a further advantage is afforded in a reduction in the lock time of the DLL circuit, i.e. a reduction in the duration until the phasing of the DLL circuit. Furthermore, the invention achieves regulation of the DLL current consumption, which is critically determined by the number of time delay changes per unit time and, on account of the filter components that are only partly activated according to the invention, is lower than in the case of constant operation of all the filter components. Finally, the synchronization circuit configured according to the invention ensures optimization of the control speed of the overall system containing circuits or computer chips.
When the filter is constructed from a plurality of counters, the activation/deactivation thereof for the purpose of changing the filter characteristic can be achieved without a great outlay by a transfer gate connected upstream of the respective counter of the filter. The transfer gate can be configured in various ways. It is preferably configured to switch on/off a specific counter or a group of counters while the remaining counters or the remaining counter remain or remains switched on. The transfer gate can be implemented cost-effectively by an n-/p-FET combination.
In accordance with an added feature of the invention, the logic circuit can be put into a test mode for setting the response sensitivity for optimizing synchronization before a control operation with a defined response sensitivity of the configuration is performed.
In accordance with another feature of the invention, the logic circuit has transfer gates connected to and switching on/off the counters in a targeted manner.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit for synchronizing signals during the exchange of information between circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.